View MC14066B_312129.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14066B Quad Analog Switch/Quad Multiplexer
The MC14066B consists of four independent switches capable of controlling either digital or analog signals. This quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS logic implementation. The MC14066B is designed to be pin-for-pin compatible with the MC14016B, but has much lower ON resistance. Input voltage swings as large as the full supply voltage can be controlled via each independent control input. * * * * * * Triple Diode Protection on All Control Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise -- 12 nV/Cycle, f 1.0 kHz typical Pin-for-Pin Replacement for CD4016, CD4016, MC14016B For Lower RON, Use The HC4066 High-Speed CMOS Device
L SUFFIX CERAMIC CASE 632
P SUFFIX PLASTIC CASE 646
D SUFFIX SOIC CASE 751A
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
II I I III I I IIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Iin Parameter DC Supply Voltage Value Unit V V - 0.5 to + 18.0 10 25 500 Vin, Vout Input or Output Voltage (DC or Transient) Input Current (DC or Transient), per Control Pin Switch Through Current - 0.5 to VDD + 0.5 mA mA Isw PD Power Dissipation, per Package Storage Temperature mW Tstg - 65 to + 150
TA = - 55 to 125C for all packages.
BLOCK DIAGRAM
CONTROL 1 IN 1 5 CONTROL 2 IN 2 CONTROL 3 IN 3 CONTROL 4 4 6 9 8 12 10 11 OUT 4 VDD = PIN 14 VSS = PIN 7 OUT 3 3 OUT 2 13 2 1 OUT 1
_C
TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN)
IN 4
VDD
VDD VDD
LOGIC DIAGRAM AND TRUTH TABLE (1/4 OF DEVICE SHOWN)
VSS IN/OUT CONTROL
Control Switch OFF ON Logic Diagram Restrictions VSS Vin VDD VSS Vout VDD
OUT/IN
VDD CMOS INPUT
VDD
VDD
VDD
300 VSS VSS
0 = VSS 1 = VDD
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14066B 1
I II I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I II I II I I I II I II I II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II II I II I IIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I II I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I II I II I I I II I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II I II I I I II I II I I I II I I I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIII I I I II I II I I I II I II I I I II I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II I II I I I II I II I I I II I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I III II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I I I II I II I II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I II I II I I I II I II I I I II I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I IIII I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHES IN AND OUT (Voltages Referenced to VSS) CONTROL INPUTS (Voltages Referenced to VSS) SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
#Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. ** For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)
ELECTRICAL CHARACTERISTICS
Capacitance, Feedthrough (Switch Off)
Capacitance, Switch I/O
Off-Channel Leakage Current (Figure 6)
ON Resistance Between Any Two Channels in the Same Package
ON Resistance
Output Offset Voltage
Recommended Static or Dynamic Voltage Across the Switch** (Figure 1)
Recommended Peak-to- Peak Voltage Into or Out of the Switch
Input Capacitance
Input Leakage Current
High-Level Input Voltage
Low-Level Input Voltage
Total Supply Current (Dynamic Plus Quiescent, Per Package
Quiescent Current Per Package
Power Supply Voltage Range
MC14066B 2
Characteristic Ch ii Vswitch Symbol S bl ID(AV) Ron VOO VDD CI/O CI/O VI/O Ron IDD VIH Cin VIL Ioff Iin VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 -- -- -- -- -- -- -- -- Control Inputs: Vin = VSS or VDD, Switch I/O: VSS VI/O VDD, and Vswitch 500 mV** Switch Off Vin = VIL or VIH (Control) Channel to Channel or Any One Channel Vswitch 500 mV**, Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) Vin = 0 V, No Load Channel On Channel On or Off Vin = 0 or VDD Ron = per spec, Ioff = per spec Ron = per spec, Ioff = per spec TA = 25_C only The channel component, (Vin - Vout)/Ron, is not included.)
v
Test C di i T Conditions
v
v
v
Min
3.5 7.0 11
3.0
--
--
--
-- -- --
-- -- --
--
--
--
-- -- --
-- -- --
0
0
- 55_C
Typical
100
0.1
VDD
0.25 0.5 1.0
Max
800 400 220
600
1.5 3.0 4.0
70 50 45
18
--
--
--
--
-- -- --
Min
(0.07 A/kHz) f + IDD (0.20 A/kHz) f + IDD (0.36 A/kHz) f + IDD
3.5 7.0 11
3.0
--
--
--
-- -- --
-- -- --
--
--
--
-- -- --
-- -- --
0
0
0.00001
MOTOROLA CMOS LOGIC DATA
0.05 Typ # 0.005 0.010 0.015 25_C 0.47 2.75 5.50 8.25 2.25 4.50 6.75 250 120 80 5.0 10 25 10 10 10 -- -- -- 100 1050 500 280 0.1 VDD 0.25 0.5 1.0 Max 600 7.5 1.5 3.0 4.0 15 70 50 45 18 -- -- -- -- -- Min 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 125_C 1000 1200 520 300 1.0 VDD Max 135 95 65 300 1.5 3.0 4.0 7.5 15 30 18 -- -- -- -- -- -- -- Vp-p Unit Ui mV V A A A nA pF pF pF V V V
II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I II III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C unless otherwise noted.)
Characteristic Symbol VDD Vdc Min Typ # Max Unit ns Propagation Delay Times Input to Output (RL = 10 k) tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns Control to Output (RL = 1 k) (Figure 2) Output "1" to High Impedance VSS = 0 Vdc tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20 10 7.0 40 35 30 40 35 30 60 20 15 60 20 15 40 20 15 80 70 60 80 70 60 tPHZ ns Output "0" to High Impedance tPLZ ns High Impedance to Output "1" tPZH 120 40 30 120 40 30 -- ns High Impedance to Output "0" tPZL ns Second Harmonic Distortion VSS = - 5 Vdc (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 k, f = 1.0 kHz) Bandwidth (Switch ON) (Figure 3) VSS = - 5 Vdc (RL = 1 k, 20 Log (Vout/Vin) = - 3 dB, CL = 50 pF, Vin = 5 Vp-p) -- 0.1 % -- 5.0 -- 65 -- MHz Feedthrough Attenuation (Switch OFF) VSS = - 5 Vdc (Vin = 5 Vp-p, RL = 1 k, fin = 1.0 MHz) (Figure 3) Channel Separation (Figure 4) (Vin = 5 Vp-p, RL = 1 k, fin = 8.0 MHz) (Switch A ON, Switch B OFF) VSS = - 5 Vdc -- -- 5.0 5.0 -- -- - 50 - 50 -- -- dB dB Crosstalk, Control Input to Signal Output (Figure 5) VSS = - 5 Vdc (R1 = 1 k, RL = 10 k, Control tTLH = tTHL = 20 ns) mVp-p -- 5.0 -- 300 -- * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
PIN ASSIGNMENT
IN 1 OUT 1 OUT 2 IN 2 CONTROL 2 CONTROL 3 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CONTROL 1 CONTROL 4 IN 4 OUT 4 OUT 3 IN 3
MOTOROLA CMOS LOGIC DATA
MC14066B 3
TEST CIRCUITS
Vout VC ON SWITCH CONTROL SECTION OF IC LOAD V Vout 10% 90% SOURCE Vout tPZL tPLZ 10% 20 ns VC tPZH Vin 90% 50% 10% RL Vx VDD CL
VSS tPHZ 90% Vin = VDD Vx = VSS Vin = VSS Vx = VDD
Figure 1. V Across Switch
Figure 2. Turn-On Delay Time Test Circuit and Waveforms
VC = VDD FOR BANDWIDTH TEST VC = VSS FOR FEEDTHROUGH TEST VDD - VSS 2 Vin RL VC CL Vout
VDD - VSS 2 Vin VDD RL CL
VSS VDD VSS
RL
CL
Figure 3. Bandwidth and Feedthrough Attenuation
Figure 4. Channel Separation
OFF CHANNEL UNDER TEST Vin Vout 1k RL 10 k VC = - 5.0 V TO + 5.0 V SWING CL = 50 pF CONTROL SECTION OF IC VDD A VSS
VSS VDD
Figure 5. Crosstalk, Control to Output
Figure 6. Off Channel Leakage
MC14066B 4
MOTOROLA CMOS LOGIC DATA
VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k VDD VSS 1 k RANGE X-Y PLOTTER
Figure 7. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS
350 R ON , "ON" RESISTANCE (OHMS) R ON , "ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 350 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 TA = 125C 25C - 55C
TA = 125C 25C - 55C
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 8. VDD = 7.5 V, VSS = - 7.5 V
Figure 9. VDD = 5.0 V, VSS = - 5.0 V
700 R ON , "ON" RESISTANCE (OHMS) RON , "ON" RESISTANCE (OHMS) 600 500 400 300 TA = 125C 200 25C 100 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 - 55C 4.0 6.0 8.0 10
350 300 250 200 150 5.0 V 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 7.5 V TA = 25C
VDD = 2.5 V
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD = 2.5 V, VSS = - 2.5 V
Figure 11. Comparison at 25C, VDD = - VSS
MOTOROLA CMOS LOGIC DATA
MC14066B 5
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0- to-5 volt digital control signal is used to directly control a 5 volt peak-to-peak analog signal. The digital control logic levels are determined by V DD and V SS. The V DD voltage is the logic high voltage, the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; V SS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and VSS. The analog voltage must not swing higher than V DD or lower than V SS. The example shows a 5 volt peak-to-peak signal which allows no margin at either peak. If voltage transients above V DD and/or below V SS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and V SS is 18.0 volts. Most parameters are specified up to 15 volts which is the recommended maximum difference between V DD and V SS.
+5 V VDD VSS + 5.0 V 5 Vp-p ANALOG SIGNAL +5 V SWITCH IN
SWITCH OUT
5 Vp-p ANALOG SIGNAL
+ 2.5 V
GND EXTERNAL CMOS DIGITAL CIRCUITRY 0-TO-5 V DIGITAL CONTROL SIGNALS MC14066B
Figure A. Application Example
VDD DX SWITCH IN DX VSS SWITCH OUT
VDD DX
DX VSS
Figure B. External Germanium or Schottky Clipping Diodes
MC14066B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01
-A-
14 9
-B-
1 7
C
L
-T-
SEATING PLANE
K F D
14 PL
G 0.25 (0.010)
M
N J TA
S 14 PL
M 0.25 (0.010)
M
TB
S
DIM A B C D F G J K L M N
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
MOTOROLA CMOS LOGIC DATA
MC14066B 7
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC14066B 8
*MC14066B/D*
MOTOROLA CMOS LOGIC DATA MC14066B/D

▲Up To Search▲

Price & Availability of MC14066B

	To Download MC14066B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .